The present invention relates to a sense amplifier and to a DRAM memory that includes the sense amplifier.
DRAM memories (Dynamic Random Access Memories) constitute an important type of memory for storing digital information. They are memories in which, after the specification of an address, data can be stored and read out again under this address. In this case, the information is stored as a quantity of charge on a capacitance. Therefore, a DRAM memory cell is constructed very simply since it can comprise merely a capacitance and a selection transistor.
DRAM memories usually have a number of DRAM memory cells which are each combined to form one or more memory cell arrays. The individual memory cells are wired to the periphery by word lines and bit lines. The bit line wiring in this case defines a grid into which read/write amplifiers are also inserted. The read/write amplifiers have the task of amplifying voltage values read from the bit lines to correspondingly predetermined levels, so that these voltage values can be evaluated and processed further in a suitable manner.
In order to read a DRAM memory cell, the latter is firstly activated via a word line. Afterwards, the memory cell can be read by the information stored in it being fed as a voltage signal via the bit line to the read/write amplifier. In order to be able to correctly evaluate the information content of the memory cell, it is furthermore necessary to compare the information read out via the bit line of the memory cell to be read, or the corresponding voltage signal, with a reference voltage signal. To that end, the read/write amplifier is furthermore connected to at least one reference bit line, which is in turn connected to a memory cell which is currently not being evaluated.
In order to be able to evaluate the voltage signals read from the memory cell to be evaluated, they must be correspondingly amplified. To that end, the read/write amplifier generally has one or more sense amplifier subcircuits. The sense amplifier subcircuit of a DRAM memory has the task of amplifying a small voltage signal, which results from the voltage level stored in the memory cell, reliably and quickly to full levels.
Depending on the information content of the memory cell to be read, the voltage level has to be amplified to a low or high level. A low level is produced by means of a sense amplifier subcircuit referred to as an N latch. A high level is produced by means of a sense amplifier subcircuit referred to as a P latch.
In the case of the xe2x80x9cmid-levelxe2x80x9d evaluation scheme which is customary nowadays, the bit line level at the beginning of the evaluation is at half the array voltage. In this case, the array voltage corresponds to the high level. Using an example, if the low level has a value of 0 volts, for example, and the high level has a value of 2 volts, for example, this means that the bit line level at the beginning of the evaluation is at 1 volt.
The sense amplifier subcircuits usually have at least two evaluation transistors which may be designed for example, but not exclusively, as xe2x80x9cfield-effect transistorsxe2x80x9d. The field-effect transistor (FET) is a semiconductor device having three terminals, which are designated by gate (G), source (S) and drain (D).
An important parameter in field-effect transistors is the xe2x80x9cthreshold voltagexe2x80x9d. This is that voltage starting from which a drain current flows in the transistor. That is to say the transistor opens. This means that, starting from the threshold voltage, the potential barrier in the transistor is reduced to such an extent that a current can flow. If a reverse voltage is applied between source and bulk, the value of the threshold voltage increases since the potential barrier increases. The bulk of the transistor is a fourth terminal, which results from the common carrier, usually a semiconductor carrier, and is also designated by substrate.
Sense amplifier subcircuits for a DRAM memory for amplifying voltage signals read from a bit line generally have at least two such evaluation transistors, the gate of one transistor being connected or connectable to at least one bit line and the gate of another evaluation transistor being connected or connectable to at least one reference bit line. Furthermore, the drains of the evaluation transistors are connected or connectable to bit lines and the sources of the evaluation transistors are connected or connectable to a lead. The lead, which is also designated as xe2x80x9cNCSxe2x80x9d in N latch sections or, respectively, is also designated as xe2x80x9cPCSxe2x80x9d in P latch sections, is a line via which the sense amplifier circuit is activated.
If, in the xe2x80x9cmid-levelxe2x80x9d evaluation scheme, the bit line level at the beginning of the evaluation is at approximately half the array voltage, this voltage level also corresponds to the gate-source voltage across the evaluation transistors. In order to achieve the evaluation with the necessary speed, the gate-source voltage must lie above the threshold voltage of the evaluation transistors by a sufficiently high magnitude. For reasons of line density and reliability, the array voltage is scaled downward with diminishing feature sizes, that is to say with advancing DRAM generations. Since the threshold voltage of the evaluation transistors cannot be reduced to the same extent as the array voltages, the distance between the initial bit line levelxe2x80x94for example half the array voltage, which corresponds to half the supply voltagexe2x80x94and the threshold voltage of the evaluation transistors becomes smaller and smaller. The evaluation transistors xe2x80x9copenxe2x80x9d less and less and the evaluation thus requires more and more time. It is very disadvantageous, however.
When xe2x80x9cSOI transistorsxe2x80x9d are used, it is possible to control the substrate potential of a transistor with a low power consumption. The designation xe2x80x9cSOIxe2x80x9d denotes xe2x80x9csilicon on insulatorxe2x80x9d. Transistors of this type have recently acquired more and more importance. SOI transistors are already known per se from the prior art.
SOI transistors open up the possibility of using a substrate control effect to influence the threshold voltage of the evaluation transistors in a positive way for the evaluation speed. The substrate, or the bulk of the transistor, is also referred to as the body in SOI transistors.
The prior art has already disclosed a number of possible solutions to enable the threshold voltage of evaluation transistors designed as SOI transistors to be influenced by means of the substrate control effect. These solutions are illustrated in FIGS. 1 to 3 and are explained in more detail in the context of the description of the figures.
In the embodiment illustrated in FIG. 1, the voltages across the sense amplifier subcircuit of a conventional sense amplifier, said subcircuit being designed as an N latch, are shown at the beginning of the evaluation operation. There is a negative voltage between source and body, said voltage increasing the threshold voltage of the transistors on account of the substrate control influence. This is disadvantageous, however, for the reasons mentioned above.
FIG. 2 illustrates the principle of xe2x80x9cbody synchronous sensingxe2x80x9d, in which the undesirable threshold voltage increase is avoided by source and body being kept at the same potential.
FIG. 3 illustrates the circuitry of the N latch section of a sense amplifier in the case of xe2x80x9csuper body synchronous sensingxe2x80x9d. The body voltage can be set via a separate line. At the beginning of the evaluation, the body voltage is set such that the source-body voltage becomes positive and the threshold voltage of the evaluation transistors is thus reduced by means of the substrate control influence. However, a positive source-body voltage means that the source-bulk diodes are forward-biased. Therefore, the sensing scheme can only be used for voltage levels at which the resulting forward current is small enough that it does not have a disadvantageous effect. The last-mentioned solution is described for example in the paper xe2x80x9cSOI-DRAM Circuit Technologies for Low Power High Speed Multi Giga Scale Memoriesxe2x80x9d by Kuge et al., IEEE Journal of Solid-State-Circuits, Vol. 31, number 4, April 1996, pages 586 ff.
Taking the abovementioned prior art as a departure point, the present invention is based on the object of further improving a sense amplifier subcircuit for a DRAM memory and also a DRAM memory in such a way that the evaluation of the memory cells can be carried out in an acceptably short time even in the case of small array voltages.
In accordance with the first aspect of the present invention, what is provided is a sense amplifier subcircuit for a DRAM memory for amplifying voltage signals read from a bit line, having at least two evaluation transistors, the gate of one evaluation transistor being connected or connectable to at least one bit line and the gate of another evaluation transistor being connected or connectable to at least one reference bit line and the drains of the evaluation transistors being connected or connectable to the bit lines and the sources of the evaluation transistors being connected or connectable to a lead. According to the invention, the sense amplifier subcircuit is characterized in that at least one of the evaluation transistors is designed in such a way that its threshold voltage changes dynamically during the evaluation operation by virtue of the change in the gate voltage being coupled to a change in the bulk voltage.
The sense amplifier subcircuit according to the invention makes it possible to evaluate the DRAM memory cells in an acceptably short time even in the case of small array voltages.
The amplifying effect of the sense amplifier subcircuit according to the invention is illustrated below with reference to an N latch section. This effect is based firstly on the fact that the evaluation transistor with the higher gate voltage discharges a capacitance connected to its drain to 0 volts more quickly than the evaluation transistor with the lower initial gate voltage. The more quickly decreasing bit line level in turn couples to the gate of the transistor which conducts more poorly anyway, and closes said transistor further.
This amplifying effect is now increased according to the invention by the threshold voltage of the transistor which conducts better being dynamically reduced, while the threshold voltage of the transistor which conducts more poorly is dynamically increased.
This dynamic change is realized by the change in the gate voltage being coupled to a change in the bulk voltage. This means that the bulk voltage changes at the same time as the gate voltage changes. The transistor which conducts better is made to conduct even better very much more quickly, while the transistor which conducts more poorly is made to conduct even more poorly very much more quickly. As a result, the evaluation time can be considerably reduced.
One advantage of the sense amplifier subcircuit according to the invention over the xe2x80x9csuper body synchronous sensingxe2x80x9d known from the prior art is that the sense amplifier subcircuit according to the invention manages without additional control lines, for instance for the N and P bodies of the P and N latches. The timing for driving the bodies (bulks) can thus be omitted. It is only by this means that the dynamic change in the threshold voltage of the at least one evaluation transistor is made possible, since the body voltage changes at the same time as and in direct dependence on the gate voltage.
For small array voltages, which may be about 0.6 to 0.9 volts for technology generations where F=70 nm and about 0.5 to 0.6 volts for F=50 nm, the sense amplifier subcircuit according to the invention enables accelerated evaluation in comparison with conventional sense amplifier subcircuits. In this case, F is understood to be the minimum lithographic feature size.
The dynamic change in the threshold voltage can advantageously be realized by the bulk (or the body) and the gate of the at least one evaluation transistor being connected to one another via a connection.
The source-drain diode of the at least one evaluation transistor is preferably forward-biased. As in the case of xe2x80x9csuper body synchronous sensingxe2x80x9d the scheme according to the invention can therefore be used for those voltage levels at which the resulting forward current is small enough that it does not have a disadvantageous effect.
The sense amplifier subcircuit according to the invention can advantageously be designed as a circuit for producing the low level (N latch) and/or as a circuit for producing the high level (P latch).
The at least one evaluation transistor can advantageously be designed as an SOI transistor. Such SOI transistors are particularly suitable since a separate region forming the bulk region (body region) is required. In the case of transistors produced in a conventional manner, although it would also be possible to produce such a body region, this would require a significantly greater outlay and would thus entail significantly higher costs, so that the use of SOI transistors is preferred.
In accordance with a second aspect of the present invention, a DRAM memory is provided, having a number of DRAM memory cells which are connected via bit lines to at least one read/write amplifier, the read/write amplifier likewise being connected to at least one reference bit line, characterized in that the read/write amplifier, for amplifying voltage signals read from a bit line, has one or more sense amplifier subcircuit(s) according to the invention as described above.
This makes it possible to evaluate the individual memory cells of the DRAM memory in an acceptably short time even in the case of small array voltages.
A sense amplifier subcircuit according to the invention as described above is used particularly preferably for evaluating small array voltages of xe2x89xa61 volt.
The invention will now be explained in more detail using exemplary embodiments with reference to the accompanying drawing, in which: